.SI Simulation

SI Simulation

Parameters sweeping
Topological definition
Static timing analysis
Transmission path optimization

Post Simulation
Reflection and crosstalk analysis report
Comprehensive timing analysis
Multi-board co-simulation

.PI Simulation

IR-Drop Analysis

Make sure the PCB traces and planes can  handle power supply requirements
IR-drop,current density and via current analysis
Electric and heat hybrid analysis 
Constraint driven design
Electrical Rules
Physics, spacing Rules
Topological Rules
Impedance rule and length match

Test and Verify
SI testing
S-Parameter measurement 
Testing report analysis

PI analysis
PDN Design of high-speed and high-power systems
Bypass capacitor selection based on time domain and frequency domain performances
Frequency Domain Target Impedance analysis

The Chicagopcb SI simulation team has 15+ years of experience in DDR4/DDR3/ DDR2 parallel bus and high speed serial bus simulation such as PCIESATASASSFP+ and 10G-KR. We provide suggestions to design the proper topology, select the best termination and driver, and optimize the whole channel to get the lowest loss and best eye open. We also have DDR4 and 25Gbps+ signal design and simulation capabilities.